Adaptive silicon synapse and CMOS neuron for neuromorphic VLSI computing
| Dublin Core | PKP Metadata Items | Metadata for this Document | |
| 1. | Title | Title of document | Adaptive silicon synapse and CMOS neuron for neuromorphic VLSI computing |
| 2. | Creator | Author's name, affiliation, country | Ziad El-Khatib; Canadian University Dubai; United Arab Emirates |
| 2. | Creator | Author's name, affiliation, country | Sherif Moussa; Canadian University Dubai; United Arab Emirates |
| 2. | Creator | Author's name, affiliation, country | Firuz Kamalov; Canadian University Dubai; United Arab Emirates |
| 2. | Creator | Author's name, affiliation, country | Mustapha C. E. Yagoub; University of Ottawa; Canada |
| 3. | Subject | Discipline(s) | Neuromorphic Computing; Artificial Intelligence |
| 3. | Subject | Keyword(s) | Adaptive silicon synapse; Neuromorphic computing; Spiking CMOS neuron; Spiking frequency modulation; Tuning synapse time-constant; |
| 4. | Description | Abstract | The design of a fully integrated adaptive modified complementary metal-oxide-semiconductor (CMOS) synapse circuit is presented. By using multiple-gated transistor configuration in the modified CMOS synapse an additional branch provide control where the synaptic output current time-constant is tuned. The effect of changing the multiple-gated transistor bias voltage from 0.25 to 0.45 V tunes the spiking output current exponential time-constant range by 200 ms as shown in simulation results. Moreover, a fully-integrated adaptive quadratic integrate-and-fire (QIF) CMOS neuron circuit is presented as well. A differential pair with variable capacitor integrator and a tunable schmitt trigger threshold detector circuit are integrated in the CMOS neuron that can be tuned varying its spiking frequency. The proposed adaptive quadratic integrate-and-fire (AQIF) neuron has the ability to adjust the spiking frequency without changing the input current. The simulation results show the proposed CMOS neuron circuit spiking frequency can be tuned from 58.4 to 312.5 Hz and its spiking period from 17.1 to 3.2 ms with tuning the bias voltage of variable capacitor integrator. Having a peak voltage Vpeak=0.95 V, a reset voltage Vreset=-0.75 V and a voltage threshold of 0.35 V with a membrane potential range of 1.5 V. The proposed CMOS neuron circuit is designed in 130 nm process with a supply voltage of 1.8 V and a total power dissipation of 1.8 mW. |
| 5. | Publisher | Organizing agency, location | Institute of Advanced Engineering and Science |
| 6. | Contributor | Sponsor(s) | University of Ottawa |
| 7. | Date | (YYYY-MM-DD) | 2025-04-01 |
| 8. | Type | Status & genre | Peer-reviewed Article |
| 8. | Type | Type | |
| 9. | Format | File format | |
| 10. | Identifier | Uniform Resource Identifier | https://ijai.iaescore.com/index.php/IJAI/article/view/25789 |
| 10. | Identifier | Digital Object Identifier (DOI) | http://doi.org/10.11591/ijai.v14.i2.pp1000-1021 |
| 11. | Source | Title; vol., no. (year) | IAES International Journal of Artificial Intelligence (IJ-AI); Vol 14, No 2: April 2025 |
| 12. | Language | English=en | en |
| 14. | Coverage | Geo-spatial location, chronological period, research sample (gender, age, etc.) | |
| 15. | Rights | Copyright and permissions |
Copyright (c) 2025 Institute of Advanced Engineering and Science This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. |