Evaluation of genetic algorithm in network-on-chip based architecture

Doraisamy Radha, Minal Moharir


An increase in the number of cores gives a significant bounce in performance than an improvement in any of the factors or hardware. Many core systems use network-on-chip (NoC) for efficient communications among the cores in the system. However, the problem with NoC-based communication is that it significantly consumes a large amount of power and energy because the number of routers increases with the increase in the number of cores in the system. Power consumed by such components leads to degradation of the performance. The placement of cores in the topology is non-deterministic polynomial-time hardness (NP-Hard) problem. The optimal placement of cores in NoC is essential as it minimizes latency and communication costs. Thus, the NP-Hard problem of placing cores is solved using genetic algorithm (GA) based quadtree topology. The proposed work shows the analysis of GA-based quadtree topology, which outperforms other topologies in most aspects. The performance evaluation of GA-based quadtree topology is based on latency, throughput, power, area, bisection bandwidth, and diameter. Comparing these parameters with other topologies shows the prominence of the quadtree topology. The evaluation is performed in the Booksim simulator, and the experimental results revealed that the proposed GA-based quad tree-based topology is efficient for NoC-based communications.


Booksim; Genetic algorithm; Latency; Network-on-chip; Power; Throughput

Full Text:


DOI: http://doi.org/10.11591/ijai.v13.i2.pp1479-1488


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

IAES International Journal of Artificial Intelligence (IJ-AI)
ISSN/e-ISSN 2089-4872/2252-8938 
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

View IJAI Stats