Performance analysis of congestion-aware Q-routing algorithm for network on chip

Smriti Srivastava, Minal Moharir, Shivaneetha Gunisetty


A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, leslie3d and bzip2 which can be used for the cores in the network in any combination. The tests were run with 16 cores on a 44 network with the maximum instruction count supported by the system (here 5,000). The proposed Q-routing algorithm showed an average of 19% reduction for benchmark simulation as compared to the Dimension-ordered (X-Y) routing for readings of average packet latency which is a crucial factor in determining a network’s efficiency. The analysis also shows an average reduction of 24%, 10%, 23% and 47% in terms of average packet network latency, average flit latency, average flit network latency and average energy consumption across various benchmarks.


Benchmark; Congestion-aware Q-routing; Network-on-chip; Q-learning; Q-routing;

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IAES International Journal of Artificial Intelligence (IJ-AI)
ISSN/e-ISSN 2089-4872/2252-8938 
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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