Serial parallel dataflow-pipelined processing architecture based accelerator for 2D transform-quantization in video coder and decoder

Abstract

The video coder and decoder (CODEC) standards from MPEG-4 to the recent versatile video codec (VVC), adopted lossy compression methodologies, which involves transformation, quantization and entropy coding. The growing usage of video data in all means of communication demands more bandwidth and storage requirements. While compression with redundancy removal by transform coefficient coding, the focal point is the crucial sequential data flow and data processing structures. Handling the block wise data near to the processing unit prior and after computation will reduce the data waiting time of the processing unit, hence accelerating the targeted functionality. The proposed serial parallel data-flow pipelined processing architecture (SPDPA) accelerates the speed of processing unit by on chip data availability and parallel data accessing options and also with the pipeline operations of transformation, data transpose and quantization. The post implementation results of the architecture targeted to 16 nm and 28 nm field programmable gate array (FPGA) shows that there is a trade-off between power and frequency of operations for various block sizes. The design targeted to 16 nm works for higher frequencies with an average power consumption 0.64 w as compared to 28 nm FPGA which consumes less average power of 0.15 w.